EDA课后习题.pptVIP

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUX41 IS PORT( s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); --输入选择信号 ???? a , b , c , d : IN STD_LOGIC; --输入信号 ???? y : OUT STD_LOGIC); --输出端 END ENTITY; ARCHITECTURE ART OF MUX41 IS BEGIN PROCESS(s) BEGIN IF (S=00) THEN y=a; ELSIF (S=01) TH EN y=b; ELSIF (S=10) TH EN y=c; ELSIF (S=11) TH EN y=d; ELSE y=NULL; END IF; EDN PROCESS; END ART; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUX41 IS PORT( s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); --输入选择信号 ???? a , b , c , d : IN STD_LOGIC; --输入信号 ???? y : OUT STD_LOGIC); --输出端 END MUX41; ARCHITECTURE ART OF MUX41 IS BEGIN PROCESS(s) BEGIN CASE s IS WHEN “00” = y=a; WHEN “01” = y=b; WHEN “10” = y=c; WHEN “11” = y=d; WHEN OTHERS = NULL; END CASE; END PROCESS; END ART; 3-3. 图3-17所示的是双2选1多路选择器构成的电路MUXK，对于其中MUX21A，当s=‘0’和‘1’时，分别有y=‘a’和y=‘b’。试在一个结构体中用两个进程来表达此电路，每个进程中用CASE语句描述一个2选1多路选择器MUX21A。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUX221 IS PORT( a1 , a2 , a3 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); --输入信号 ???? s0 , s1 : IN STD_LOGIC; ???? outy : OUT STD_LOGIC); --输出端 END ENTITY; ARCHITECTURE ONE OF MUX221 IS SIGNAL tmp : STD_LOGIC; BEGIN PR01:PROCESS(s0) BEGIN CASE s0 IS when ‘0’ = tmp = a2; when ‘1’ = tmp = a3; when others = NULL; END CASE; END PROCESS; PR02:PROCESS(s1) BEGIN CASE s1 IS when ‘0’ = outy = a1; when ‘1’ = outy = tmp; when others = NULL; END CASE; END PROCESS; END ARCHITECTURE ONE; LIBR