27256中文资料.pdf

M74HC51 DUAL 2 WIDE 2 INPUT AND/OR INVERT GATE HIGH SPEED: tPD = 11ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 1µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.) DIP SOP TSSOP SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: ORDER CODES tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: PACKAGE TUBE T R VCC (OPR) = 2V to 6V DIP M74HC51B1R PIN AND FUNCTION COMPATIBLE WITH SOP M74HC51M1R M74HC51RM13TR 74 SERIES 51 TSSOP M74HC51TTR DESCRIPTION The internal circuit is composed of 3 stages (2 The M74HC51 is an high speed CMOS DUAL 2 INPUT) or 5 stages (3 INPUT) including buffer WIDE 2 INPUT AND/OR INVERT GATE output, which enables high noise immunity and 2 fabricated with silicon gate C MOS technology. stable output. It contains a 2-WIDE 2-INPUT AND/OR INVERT All inputs are equipped with protection circuits GATE and a 2-WIDE 3-INPUT AND/OR against static discharge and transient excess INVERT GATE. voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS August 2001 1/9 M74HC51 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL