Intel微机原理第10章(存储器接口)-2.ppt

生物 1. Memory Devices RAM SRAM DRAM ROM ROM PROM EPROM EEPROM (Flash Memory) 存储器引脚 地址线---- All memory devices have address inputs select a memory location. Three main points: ? arrange number ? the number of memory locations found ? first address and last address 存储器引脚图 EPROM 2716 (2kX8) 2716读时序 SRAM 4016 (2Kx8) DRAM 4464 (64K X 4) 4464时序 Difference between SRAM and DRAM SRAMs are limited in size (up to 128K X 8). DRAMs are available in much larger sizes, e.g., 16M X1, 64M X 1 256M X 1. DRAMs must be refreshed every 2 to 4 ms. DRAMs are typically placed on SIMM (Single In-line Memory Modules)boards.（单列直插式存储器模块） 30-pin SIMMs come in 1M X 8, 1M X 9 (parity), 4M X 8, 4M X 9. 72-pin SIMMs come in 1/2/3/8/16M X 32 or 1M X 36 (parity). See p343 fig.10-11 SIMM and DIMM Pentiums have a 64-bit wide data bus. 64-bit DIMMs (Dual In-line Memory Modules) are the standard. （双列直插式存储器模块） The board has DRAMs mounted on both sides and is 168 pins. Sizes include 2M X 64 (16M), 4M X 64 (32M), 8M X 64 (64M) and 16M X64 (128M). See p344 fig.10-12 The DIMM module is available in DRAM, EDO and SDRAM with and without an EPROM. The EPROM provides information about the size and speed of the memory device for PNP applications. 2.Address Decoding 存储器地址译码使存储器工作在存储器映射表中独立的区域，CPU按地址访问其存储单元 (location),访问方法可采用字节寻址或字寻址。 地址译码需要地址译码器，CPU的地址线通过地址译码器与存储器连接。 地址译码可采用3-8译码器、PROM地址译码器、PLD地址译码器等技术。 Simple NAND Gate Decoder Address location The 3-to-8 Line Decoder Decoder Circuit PROM Address DecoderTPB28L42 (512X8) PLD Programmable Decoder PLDs come in three varieties: ? PLA (Programmable Logic Array) ? PAL (Programmable Array Logic) ? GAL (Gated Array Logic) A PAL example (16L8) is shown in the text and is commonly used to decode the memory address, particularly for 32-bit addresses generated by the 80386DX and above. AMD 16L8 PAL PAL 16L8译码器--8X2764（8KX8） 3 .8088 And 80188 Memory Interface 8088 and 80188 (8-bit) Memory Interface The memory