Quartus II宏模块的中英对照（国外英文资料）.docVIP

Quartus II宏模块的中英对照（国外英文资料） RAM macroblock The macro module name function description The csdpram parameterized loop shares dual port RAM The lpm_ram_dp parameterized dual port RAM The lpm_ram_dq parameterized RAM and the input/output ends are separated The lpm_ram_io parameterized RAM and the input/output port public one port FIFO macroblock The macro module name function description The csfifo parameterized loop shares FIFO Dcfifo parameterized dual clock FIFO Scfifo parameterized single clock FIFO The lpm_fifo parameterized single clock FIFO The lpm_fifo_dc parameterized dual clock FIFO The design of the ROM lpm_rom The Quartus II development softwares macro module, the time series circuit macromodule, Quartus II, develops the macro module in the software, the time series circuit macromodule The trigger The macro module name function description Lpm_ff parameterized D or T triggers Lpm_dff parameterized D triggers and shift registers The lpm_tff parameterized T trigger The enadff band enables the capable D trigger The D trigger that expdff implements with an extended circuit 7470 with the preset and the clear zero and the door JK trigger The JK trigger with the preset side of the band 7471 7472 with the preset and the clear zero and the door JK trigger 7473 with a pure zero double JK trigger The two-d flip-flop with asynchronous preset and asynchronous zero 7476 with both asynchronous preset and asynchronous zero-point double JK triggers 7478 the dual JK trigger with asynchronous preset, public zero, and public clock 74107 the double JK trigger with the clear zero 74109 with the double JK trigger on the preset and the clear zero The double JK clock of the preset and the liquid-zero is down the trigger The double JK clock on the preset side of the band falls along the trigger 74114 the double JK clock on the asynchronous preset, public, and public clock is down the trigger 74171 the 4D trigger with the clear zero A multi-port register with a three-state output in 7