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汇编选择（国外英文资料）
汇编选择（国外英文资料）
Chapter 1 basics
(1) a CPU has a addressing capability of 8KB, so the width of its address bus is 4.
1, 8
2, 10,
3, 12
4, 13
(2) the bus is logically divided into three classes, and the following options are not included: 2.
Data bus
Parallel bus
Address bus
Control the bus
(3) the addressable capacity of 1 CPU is 32KB, so the width of its address bus is 2.
1, 13
2, 15
3, 18
4, 32 k
(4) one CPU reads 1024 bytes of data at least 512 times, the width of the data bus 3.
1, 8
2, 10,
3, 16
4, 32
(5) the maximum memory address of 1 CPU is 1023, the width of the address bus 2.
1, 8
2, 10,
3, 13
4, 14
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Chapter 2 registers (how the CPU works)
(1) the following address information differs from the memory address defined by 0020H: 03EFH.
1, 5 efh
2, 203 h: 00 efh
3, 005 eh: 000 fh
4, 0002 h: 05 CFH
(2) the data in AX after the instruction execution is: 2.
Mov ax, 936 ah
Mov bx, 79 b8h
The add al, bl
1, 1, c22h
2, 9322 h
3, 9422 h
4, 1 d22h
(3) the CPU starts execution at 1000:0 the CPU changes IP 3 several times after the instruction that executes 1000:10.
1000:0 mov ax, 8
1000:3 JMP ax
1000:5 mov ax, 0
1000:8 mov bx, ax
1000:10 JMP bx
1, 4,
2, 5
3, 6
4, 7
(4) in DEBUG, the command in the 1 option modifies the contents of the memory unit
1, a.
2, d
3, t
4, and u
(5) the following statement is correct: 4.
After an instruction is executed, the value of the IP is changed.
When the CPU executes the current instruction, the CPU is idle and no longer works.
The e command changes the data in all memory units.
The CPU will execute the data in the memory unit that the IP is pointing to.
(6) the following description of the working principle of 8086CPU is incorrect.
Assembly programmers can control the CPU by modifying the contents of various registers.
When the CPU is accessing memory, the physical address of the memory unit
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