10VHDL语句(完全)1.ppt

EDA技术与VHDL ;10.1 顺序语句(Sequential Statements) ;【例10-1】 LIBRARY IEEE； USE IEEE.STD_LOGIC_1164.ALL； ENTITY mux41 IS PORT (s4，s3, s2，s1 : IN STD_LOGIC; z4，z3, z2，z1 : OUT STD_LOGIC); END mux41； ARCHITECTURE activ OF mux41 IS SIGNAL sel : INTEGER RANGE 0 TO 15; BEGIN PROCESS (sel ，s4，s3，s2，s1 ) BEGIN sel= 0 ; -- 输入初始值 IF (s1 =1) THEN sel = sel+1 ; ELSIF (s2 =1) THEN sel = sel+2 ; ELSIF (s3 =1) THEN sel = sel+4 ; ELSIF (s4 =1) THEN sel = sel+8 ; ELSE NULL; -- 注意，这里使用了空操作语句 END IF ; z1=0 ; z2=0; z3=0; z4=0; --输入初始值 CASE sel IS WHEN 0 = z1=1 ; -- 当sel=0时选中 WHEN 1?3 = z2=1 ; -- 当sel为1或3时选中 WHEN 4 To 7?2 = z3=1; -- 当sel为2、4、5、6或7时选中 WHEN OTHERS = z4=1 ; -- 当sel为8～15中任一值时选中 END CASE ； END PROCESS ； END activ ； ;10.1 顺序语句(Sequential Statements) ;【例10-3】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY alu IS PORT( a, b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); opcode: IN STD_LOGIC_VECTOR (1 DOWNTO 0); result: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END alu; ARCHITECTURE behave OF alu IS CONSTANT plus : STD_LOGIC_VECTOR (1 DOWNTO 0) := b00; CONSTANT minus : STD_LOGIC_VECTOR (1 DOWNTO 0) := b01; CONSTANT equal : STD_LOGIC_VECTOR (1 DOWNTO 0) := b10; CONSTANT not_equal: STD_LOGIC_VECTOR (1 DOWNTO 0) := b11; BEGIN PROCESS (opcode,a,b) BEGIN CASE opcode IS WHEN plus = result = a + b; -- a、b相加 WHEN minus = result = a - b; -- a、b相减 WHEN equal = -- a、b相等 IF (a = b) THEN result = x01; ELSE result = x00; END IF; WHEN not_equal = -- a、b不相等 IF (a /= b) THEN result = x01; ELSE result = x00; END IF; END CASE; END PROCESS; END