8vhdl语句.pptVIP

EDA技术实用教程;;8.1.1 赋值语句;【例】 SIGNAL S1,S2:STD_LOGIC; SIGNAL SVEC:STD_LOGIC_VECTOR(0 TO 7); … PROCESS(S1,S2) VARIABLE V1,V2:STD_LOGIC; BEGIN V1 := ‘1’; V2 := ‘1’; S1 = ‘1’; S2 = ‘1’; SVEC(0) = V1; SVEC(1) = V2; SVEC(2) = S1; SVEC(3) = S2; V1 := ‘0’; V2 := ‘0’; S2 = ‘0’; SVEC(4) = V1; SVEC(5) = V2; SVEC(6) = S1; SVEC(7) = S2; END PROCESS; ;2、赋值目标;8.1.2 IF 语句;【例】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY control_stmts IS PORT (a, b, c: IN BOOLEAN; output: OUT BOOLEAN); END control_stmts; ARCHITECTURE example OF contr