第六章典型数字系统设计.ppt

第六章 典型数字系统设计 ;分频电路;偶数分频 ;ARCHITECTURE a OF div_fre IS SIGNAL cnt: STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL div_tmp:STD_LOGIC; BEGIN PROCESS (clk) BEGIN IF (rst=1) THEN cnt=0000; ELSIF (clk’EVENT AND clk=1) THEN IF (cnt=1111) THEN cnt= (OTHERS=0); div_tmp=1; ELSE cnt=cnt+1; div_tmp=0; END IF; END IF; END PROCESS; div_out=div_tmp; END a;;奇数分频 ;ARCHITECTURE a OF div_fre IS SIGNAL cnt: STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL div_tmp:STD_LOGIC; BEGIN PROCESS (clk) BEGIN IF (rst=1) THEN cnt=0000; ELSIF (clk’EVENT AND clk=1) THEN IF (cnt=1110) THEN div_tmp=NOT div_tmp; cnt= (OTHERS=0); ELSIF (cnt=0111) THEN div_tmp=NOT div_tmp; cnt= cnt+1; ELSE cnt=cnt+1; END IF; END IF; END PROCESS; div_out=div_tmp; END a;;LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY div_fre IS PORT (clk：IN STD_LOGIC; rst：IN STD_LOGIC; div_out：OUT STD_LOGIC); END div_fre; ARCHITECTURE a OF div_fre IS SIGNAL cnt1,cnt2: STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL div_tmp1,div_tmp2:STD_LOGIC; BEGIN PROCESS (clk,rst) BEGIN IF (rst=1) THEN cnt1=0000; ELSIF (clk’EVENT AND clk=1) THEN IF (cnt1=1110) THEN div_tmp1=NOT div_tmp1; cnt1= (OTHERS=0); ELSIF (cnt1=0111) THEN div_tmp1=NOT div_tmp1; cnt1= cnt1+1; ELSE cnt1=cnt1+1; END IF; END IF; END PROCESS; PROCESS(clk,rst) BEGIN IF (rst=1) THEN cnt2=0000; ELSIF (CLK’EVENT AND CLK=0) THEN IF (cnt2=1110) THEN div_tmp2=NOT div_tmp2; cnt2= (OTHERS=0); ELSIF (cnt2=0111) THEN div_tmp2=NOT div_tmp2; cnt2= cnt2+1; ELSE cnt2=cnt2+1; END IF; END IF; END PROCESS; div_out=div_tmp1 OR div_tmp2; END a;; X.5分频 ; 采用VHDL编程实现分频系数为N=6.5的分频器，可采用以下方法：首先进行模7的计数，在计数到6时，将输出时钟赋为1，并且将计数值清零。这样，当计数值为6时，输出时钟才为1，只要再设计一个扣除脉冲电路，每到7个脉冲就扣除一个脉冲，即可实现6+0.5分频时钟。 ;LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC