VHDL序检测器.docVIP

课程：VHDL数字系统设计与测试 题目：序列检测器（1110010） 功能：输入一个串行位流，当出现“1110010”时，输出为1，其它输出为0 设计思路：通过状态机来实现序列检测器 状态机转移图（quartus） 具体的VHDL代码： library ieee; use ieee.std_logic_1164.all; //VHDL库声明 entity sequence_dectector is port(clk,rst,d: in bit; q: out bit); end sequence_dectector; //实体定义及输入输出 architecture behavior of sequence_dectector is //构造体部分 type state is (state1,state2,state3,state4,state5,state6,state7,state8); signal present_state ,next_state: state; //定义枚举数据类型 begin // 状态机时序逻辑部分的设计 process(rst , clk) begin if(rst = 1) then present_state = state1; // 复位有效时，状态变为state1 elsif(clkevent and clk = 1) then present_state = next_state; // 复位无效时，时钟上升沿状态更新 end if; end process; //状态机中组合逻辑部分的设计 process(d , present_state) //状态不同时，输出也不同，根据d的不同来确定下一状态 begin case present_state is when state1 = q = 0; if(d = 1) then next_state = state2; else next_state = state1; end if; when state2 = q = 0; if(d = 1) then next_state = state3; else next_state = state1; end if; when state3 = q = 0; if(d = 1) then next_state = state4; else next_state = state1; end if; when state4 = q = 0; if(d = 0) then next_state = state5; else next_state = state4; end if; when state5 = q = 0; if(d = 0) then next_state = state6; else next_state = state2; end if; when state6 = q = 0; if(d = 1) then next_state = state7; else next_state = state1; end if; when state7 = q = 0; if(d = 0) then next_state = state8; else next_state = state3; end if; when state8 = //此时检测到1110010，输出为1 q = 1; if(d = 0) then next_state = state1; else next_state = state2; end if; end case; end process; end behavior; quartus的功能仿真图 有功能仿真图可知代码实现了要求的序列检测器的要求