线性模式开关电容DC-DC变换器的混沌控制-enhancement详解.PDF

DESIGN OF A CAPACITOR-LESS LOW-DROPOUT VOLTAGE REGULATOR X. R. LI, D.B. PEI, Q. LIU and R.SHEN Institute of Electronic CAD, Xidian University, No. 2, South Tai Bai Road, Xi'an 710071, P R China lixianrui4213@126.com Received (Day Month Year) Revised (Day Month Year) Accepted (Day Month Year) A solution to the stability of capacitor-less low-dropout regulators with a 4pF Miller capacitor in Multi-level current amplifier is proposed. With the Miller compensation, a more than 50°phase margin is guaranteed in full load. An extra fast transient circuit is adopted to reduce stable time and peak voltage. When the load changes from light to heavy, the peak voltage is 40mV and chip quiescent current is only 45uA. Key words: LDO; SoC; capacitor-less; transient enhancement. 1．Instruction Multiple Low-Dropout-Regulators (LDO) are often used for power management in multi-core designs or System-on-Chip (SoC) applications. As the number of LDOs used in such systems may be dozens, the number of on- and off-chip component required by every single LDO directly affects the total chip area, pins of package, and thus cost of the system. However, it is well known that LDO suffers intrinsic stability problem and requires a relatively large capacitor for frequency compensation [1-5]. This compensation capacitor, whether on or off-chip, makes full integration of LDO difficult if not impos