ADSP基础入门 第3讲 ADSP处理器的外设.pptVIP

Support E-mail: china.dsp@ Support E-mail: china.dsp@ ADSP-BF533 Peripherals ADSP-BF533 Peripherals 1. DMA Controllers 2. PF (PF即为Programmable Flags ，也就是GPIO) 3. PPI (最大速率可达SCLK/2的可编程并行总线,可与视频CODEC连接) 4. SPI (提供速度高达SCLK/4的同步串行通信) 5. SPORTS (能够以最大可达SCLK/2的速度进行高速同步串行通信) 6. UART (最大波特率SCLK/16，主要负责与外围慢速串行设备连接) 7. Timer/Counters Real-Time Clock (RTC 为处理器提供数字钟) Watchdog Timer (按SCLK工作，如果在程序更新前停止计数，会产生一个事件) Core Timer (按CCLK工作,产生用于各种系统定时功能的周期性中断) General Purpose Timers (PWM、定时、给外部事件计数等) 8. EBIU外部总线接口单元(提供与外部存储器的无缝连接) 9. Others Debug/JTAG Interface Event Handler On-Chip PLL Capable of 1x To 63x Frequency Multiplication ADSP-BF533 Core Registers  Core registers accessed by name Data Registers: R0-R7 Accumulator Registers: A0, A1 Pointer Registers: P0-P5, FP, SP,USP DAG Registers: I0-I3, M0-M3, B0-B3, L0-L3 Cycle Counters: Cycles, cycles2 Program Sequencer: SEQSTAT System Configuration Register: SYSCFG Loop Registers: LT[1:0], LB[1:0], LC[1:0] Interrupt Return Registers: RETI, RETX, RETN, RETE SYSCFG Register The System Configuration register (SYSCFG) controls the configuration of the processor. This register is accessible only from the Supervisor mode. Registers ADSP-BF533 Register Groups (MMR Based) Core Memory-mapped Registers L1 Data Memory Registers L1 Instruction Memory Registers Core Timer Registers Core Interrupt Controller Registers Debug Registers System Memory-mapped Registers Watchdog Timer Registers Timer Registers RTC Registers etc. Memory Mapped Registers (MMRs)  A majority of registers are memory mapped and must be accessed indirectly Core MMRs are used to configure the core registers They are listed in Appendix A of the HRM. All Core MMRs must be accessed with 32-bit reads or writes. System MMRs are used to configure all other peripherals They are listed in Appendix B of the HRM. Some System MMRs must be accessed with 32-bit reads or writes and others with 16-bit reads or writes (See the HRM for details). The addresses of the co