语法总复习解析.ppt

可综合设计——设计准则3 用组合逻辑实现的电路和用时序逻辑实现的电路要分配到不同的进程中。 Integer应加范围限制。 通常的可综合代码应该是同步设计。 避免门级描述，除非在关键路径中。 有限状态机 存状态机是绝大部分控制电路的核心结构 有限状态机可以使用always语句和case语句描述，状态保存在寄存器中，根据寄存器不同的值（状态）执行不同的操作，case语句的多个分支则代表了不同状态的行为 moore有限状态机：输出仅依赖于内部状态，跟输入无关 mealy有限状态机：输出不仅决定于内部状态，还跟外部输入有关 moore有限状态机实例 module moore_fsm(clk, reset, A, Z, finish); parameter STATE_INIT = 0; parameter STATE_ST1 = 1; parameter STATE_ST2 = 2; parameter STATE_FINISH = 3; input clk, reset; input A; output [1:0] Z; output finish; reg [1:0] state; reg [1:0] Z; reg finish always @(negedge reset or posedge clk) begin if(!reset) begin state = STATE_INIT; Z = 2b00; finish = 1b0; end else begin case(state) STATE_INIT: begin state = STATE_ST1; Z = 2b01; finish = 1b0; end STATE_ST1: begin if(A) state = STATE_ST2; else state = STATE_FINISH; Z = 2b11; finish = 1b0; end STATE_ST2: begin state = STATE_FINISH; Z = 2b10; finish = 1b0; end STATE_FINISH: begin //state = STATE_FINISH; Z = 2b01; finish = 1b1; end endcase end end endmodule STATE_ST1 STATE_INIT STATE_ST2 STATE_FINISH reset=1, A = 1 reset=1, A = 0 reset = 0 reset = 1 reset=1 reset=1 reset = 0 reset = 0 mealy有限状态机实例 module mealy_fsm(clk, reset, A, Z, finish); parameter STATE_INIT = 4’b0001; parameter STATE_ST1 = 4’b0010; parameter STATE_ST2 = 4’b0100; parameter STATE_FINISH = 4’b1000; input clk, reset; input A; output [1:0] Z; output finish; reg [3:0] current_state, next_state; reg [1:0] Z; reg finish; always @(negedge reset or posedge clk) begin if(!reset) current_state = STATE_INIT; else current_state = next_state; end always @(currenet_state or A) begin finish = 1b0; case(current_state) STATE_INIT: begin next_state = STATE_ST1; Z = 2b01; en