基于VHDL的TLV5630串行DAC程序.docVIP

基于VHDL的TLV5630串行DAC程序 电路： 芯片串行接口时序 TLV5630是串行12位DAC，8通道输出，具体可以看datasheet，一次传输16位，第15~12位是内部寄存器地址位，第11~0位是数据位。按照此电路的接法，要想能有电压输出，必须要配置寄存器CTRL0，具体可见下图。 顶层： library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity serial_dac is port( clk,rst:in std_logic; sta:in std_logic; datain:in std_logic_vector(15 downto 0); sck:out std_logic; sdo:out std_logic; f:out std_logic ); end serial_dac ; architecture Behavioral of serial_dac is component cont_5 port( clk,rst:in std_logic; en,ld:in std_logic; dq:out std_logic_vector(2 downto 0); co:out std_logic ); end component; signal dq_bit,dq:std_logic_vector(3 downto 0); signal rw_busy: std_logic; signal rw_end:std_logic; signal ld_tmp:std_logic; signal dq_tmp:std_logic_vector(2 downto 0); signal en:std_logic; signal sck_reg:std_logic; signal tr_data:std_logic_vector(15 downto 0); signal f_reg:std_logic; begin rw_end=en and dq_bit(3) and dq_bit(2) and dq_bit(1) and dq_bit(0); sck=sck_reg; ld_tmp=not(sta or rw_end); sdo=tr_data(15); f=f_reg; uo:cont_5 port map(clk,rst,rw_busy,ld_tmp,dq_tmp,en); process(clk,rst) begin if(rst=0)then f_reg=1; elsif(clkevent and clk=1)then if(rw_busy=1 and dq_bit=0000)then f_reg=0; else f_reg=1; end if; end if; end process; process(clk,rst) begin if(rst=0)then rw_busy=0; elsif(clkevent and clk=1)then if((sta=1 and rw_busy=0) or (rw_busy=1 and rw_end=1))then rw_busy=not rw_busy; end if; end if; end process; process(clk,rst) begin if(rst=0)then dq_bit=x0; elsif(clkevent and clk=1)then if((rw_busy=0 and sta=1) or (en=1 and dq_bit=xf))then dq_bit=x0; elsif(rw_busy=1 and en=1)then dq_bit=dq_bit+1; end if; end if; end process; process(clk,rst) begin if(rst=0)then sck_reg=0; elsif(clkevent and clk=1)then if(rw_busy=1)then if(dq_tmp=000 or dq_tmp=001 or dq_tmp=010)then sck_reg=1; else sck_reg=0; end