AD7705应用总结(国外英语资料).doc

AD7705应用总结 AD7705 application summary [transfer]: The YW2314R12 project uses AD7705, which summarizes the application experience of AD7705 and the main points of attention as follows: these experiences are also applicable to the AD chips of AD company such as AD7799 and AD7706, which have calibration functions. 1. time points: when the digital interface lost can last 32 pulse cycles through the ADIN input (DCLK) high level above the digital interface of AD7705 reset, reset after waiting more than 500us to access the AD7705 chip, this reduction does not affect any register of the AD7705 department, all registers will remain before the return of the the content, but all of the registers in the digital interface lost state content is uncertain, it is strongly recommended that all internal AD7705 reset register after reset, to prevent errors. The reset of the chip pin RESET will restore all the registers in the chip to the default value of power on. The clock input signal DCLK is a Schmidt start signal that is adapted to the slow edge of the optocoupler, and the rise and fall times of other digital input signals should not exceed 1us. When the 2.AD7705 clock is greater than 2M, the CLK bit of the clock setting register should be set at 1, and the 2M should be set at less than 0. DCLK pulse width to meet the minimum pulse width requirements. The data ADOUT is read during the low level after the clock DCLK drops. During the low level of the clock DCLK, the data is written to the ADIN, and then written to the 7705 on the rising edge of the DCLK. Write data and read data of the number of clock DCLK and (to be written or read registers) number of the same length (more or less than the length of the clock register bit) DCLK number will lead to wrong operation. In between the two write operation, ADIN should be best kept at high level: because any (read or write) operations must start from the written communication and written communication register register, 8 bits of the fir