The Stanford FLASH multiprocessor：（斯坦福FLASH多处理器）.pdfVIP

The Stanford FLASH Multiprocessor Jeffrey Kuskin, David Ofelt, Mark Heinrich, John Heinlein, Richard Simoni, Kourosh Gharachorloo, John Chapin, David Nakahira, Joel Baxter, Mark Horowitz, Anoop Gupta, Mendel Rosenblum, and John Hennessy Computer Systems Laboratory Stanford University Stanford, CA 94305 Abstract in functions performed by the node controller. In both The FLASH multiprocessor efficiently integrates support for cases, the primary performance-critical function of the cache-coherent shared memory and high-performance message node controller is the movement of data at high bandwidth passing, while minimizing both hardware and software overhead. and low latency among the processor, memory, and net- Each node in FLASH contains a microprocessor, a portion of the work. In addition to these existing similarities, the archi- machine’s global memory, a port to the interconnection network, tectural trends for both styles of machine favor further an I/O interface, and a custom node controller called MAGIC. convergence in both the hardware and software mecha- The MAGIC chip handles all communication both within the node and among nodes, using hardwired data paths for efficient nisms used to implement the communication abstractions. data movement and a programmable processor optimized for Message-passing machines a