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各种电平标准的讨论(TTL,ECL,PECL,LVDS,CMOS,CML)(国外英文资料)
各种电平标准的讨论(TTL,ECL,PECL,LVDS,CMOS,CML)
The most distinctive feature of ECL circuits is that their basic gate circuits operate in a state of unsaturation, so the maximum of the ECL circuit
The advantage is that the average delay time of this circuit can be up to several nanoseconds or even nanoseconds
Magnitude, which makes the ECL integrated circuit play an unmatched role in high-speed and ultra high-speed digital systems.
The logic swing of the ECL circuit is small (only about 0.8V, while the logic swing of the TTL is about 2.0V)
When the circuit transits from one state to another, the charge and discharge time of the parasitic capacitor will be reduced
ECL circuits have important reasons for high switching speed. But the logic swing is small and the anti-interference ability is disadvantageous.
Since the switch of the unit gate is rotated in turn, there is no cut-off state for the whole circuit
The power consumption of the unit circuit is larger.
From the logic function of the circuit, the ECL integrated circuit has complementary outputs, which means simultaneous gain
There are two logic level outputs, which will greatly simplify the design of logic systems.
The switch of the ECL integrated circuit has a great feedback resistance, and it is the emitter follower output,
Therefore, this circuit has very high input impedance and low output impedance. The emitter follower outputs also have the right logic
Buffer function of signal.
TTL and CMOS circuits are widely used in general electronic device devices. But now the face of increasingly complex systems, the amount of data transmission more and more real-time requirements more and more high, the development trend of the long transmission distance and high speed data transmission, master the logic level of knowledge and design ability is more urgent.
1, several commonly used high-speed logic level
1.1LVDS level
LVDS (Low Voltage Differential Signal), that is, low-voltage differential signal, LVDS interface, also known
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