组合逻辑电路设计设计05(第五章Bvhdl基本语素、语法、语句)试卷.ppt

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Mealy型-标准形式程序代码 entity Mealy_S is port(d,clk:in std_logic; y:out std_logic); end Mealy_S; architecture bh of Mealy_S is type StateTTT is (s0,s1,s2); signal current_state,exitation :StateTTT; begin p0:process(clk) begin if(clkevent and clk=1)then current_state=exitation; end if; end process p0; p1:process(current_state,d) begin case current_state is when s0= if(d=0)then exitation=s0; else exitation=s1; end if; when s1= if(d=0)then exitation=s0; else exitation=s2; end if; when s2= if(d=0)then exitation=s0; else exitation=s2; end if; when others= exitation=s0; end case; end process p1; p2:process(current_state,d) begin case current_state is when s2= if(d=0)then y=1; else y=0; end if; when others= y=0; end case; end process p2; --y=1 when current_state=s2 and d=0 else 0; end bh; 判断进程语句?组合 OR 时序 Process() Begin If(clk’event and clk=‘1’)then End if; End process; 内部是否有上升沿判断 序列信号：110 序列检测器 CLK Z x Rst 状态机自启动：RST复位控制 LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY sqs IS PORT( Rst,x,clk: in Std_logic; z: out Std_logic); END sqs; ARCHITECTURE a OF mealy IS TYPE STATE_TYPE IS (s0, s1, s2); SIGNAL state: STATE_TYPE; BEGIN PROCESS (rst,clk) BEGIN If (Rst=‘1’) then state=s0; elsif （clk‘EVENT AND clk = ’1‘） then CASE state IS WHEN s0 = IF din=‘1’ THEN state = s1; else state=s0; END IF; WHEN s1 = IF din=‘1 THEN state = s2; else state=s0; END IF; WHEN s2 = IF din=0 THEN state=s0; else state=s2; END IF; WHEN others = state=s0; END CASE; End if; END PROCESS; z=1 when (state=s2 and