初学者——数电基本知识.pptVIP

逻辑门 3-1 The Inverter (The NOT Gate)反相器(非门) NOT Gate  Figure 3–3 Timing diagram for the case in Figure 3–2. Figure 3–4 Determine the output corresponding to the input and show the diagram. Figure 3–6 The inverter complements an input variable. 3-2 The AND Gate与门 Figure 3–9 All possible logic levels for a 2-input AND gate. Open file F03-09 to verify AND gate operation. Figure 3–10 Example of AND gate operation with a timing diagram showing input and output relationships. Figure 3–72 3-3 The OR Gate 或门 OR gate with multiple inputs Figure 3–20 Example of OR gate operation with a timing diagram showing input and output time relationships. Figure 3–24 A simplified intrusion detection system using an OR gate. 3-4 The NAND Gate与非门 3-5 The NOR Gate或非门 Figure 3–37 Standard symbols representing the two equivalent operations of a NOR gate. 3-6 Exclusive-OR 异或门 3-7 Exclusive-NOR Gate 同或门 Figure 3–61 Pin configuration diagrams for some common fixed-function IC gate configurations. Figure 3–65 The partial data sheet for a 74LS00. perform：履行，完成 inhibit ：抑制，阻止 second秒 intrusion indicate:指示,标示 tank盛 液体或气体的大容器,水池 indication:指示,表示 与逻辑：决定事件发生的各条件中，所有条件都具备，事件才会发生（成立）。be defined as,,,definition 与逻辑：决定事件发生的各条件中，所有条件都具备，事件才会发生（成立）。 definition be defined as或逻辑：决定事件发生的各条件中，有一个或一个以上的条件具备，事件就会发生（成立） pin Slide * FloydDigital Fundamentals, 9/e Copyright ?2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved. 3-1 The Inverter/ The NOT Gate（非门） 3-2 The AND Gate（与门） 3-3 The OR Gate（或门） 3-4 The NAND Gate（与非门） 3-5 The NOR Gate（或非门） 3-6 The Exclusive-OR Gate（异或门） 3-7 The Exclusive-NOR Gate（同或门） The output of an inverter is always the complement (opposite) of the input. Boolean expression Truth table 0 = LOW1 = HIGH Truth table:真值表 Boolean expression:布尔(逻辑)表达式 IEEE: Institute of Electrical and Electronics