时钟切换电路(精)资料.pdf

Techniques to make clock switching glitch free Techniques to make clock switching glitch free By Rafey Mahmud, EEdesign June 30, 2003 (1:08 p.m. EST) URL: /story/OE0035 With more and more multi-frequency clocks being used in todays chips, especially in the communications field, it is often necessary to switch the source of a clock line while the chip is running. This is usually implemented by multiplexing two different frequency clock sources in hardware and controlling the multiplexer select line by internal logic. The two clock frequencies could be totally unrelated to each other or they may be multiples of each other. In either case, there is a chance of generating a glitch on the clock line at the time of the switch. A glitch on the clock line is hazardous to the whole system, as it could be interpreted as a capture clock edge by some registers while missed by others. In this article, two different methods of avoiding a glitch at the output clock line of a switch are presented. The first method is used when clocks are multiples of each other, while the second deals with clocks totally unrelated to each other. The problem with on-the-fly clock switching Figure 1 shows a simple implementation of a clock switch, using an AND-OR type multiplexer logic. The multiplexer has one control signal, named SELECT, which either propagates CLK0 to the output when set to zero or propagates CLK1 to the output when set to one. A glitch may be caused due to immediate switching of the output from Current Clock source to the Next Clock source, when the SELECT value changes. Current Clock is the clock source currently selected while Next Clock is the clock source corresponding to the new SELECT value. The timing diagram in Figure 1 shows how a glitch is generated at the output, OUT CLOCK, when the SELECT control signal changes. The problem with this kind of switch is that the switch control signal can change any time with respect to the sourc