第5章_Testbench与Modelsim.ppt

加入信号 * 仿真波形 * FPGA系统设计 第5章 Testbench与ModelSim * 数字设计的验证已经成为一个日益困难和繁琐的任务。验证工程师们依靠一些验证工具和方法来应付这个挑战。对于几百万门的大型设计，工程师们一般使用一套形式验证（formal verification）工具。然而对于一些小型的设计，用testbench就可以很好地进行验证。 通常testbench用工业标准的VHDL或Verilog硬件描述语言来编写。Testbench调用待测功能设计，然后进行仿真。 * Testbench实例 LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mlu IS PORT( NEG_A : IN STD_LOGIC; NEG_B : IN STD_LOGIC; NEG_Y : IN STD_LOGIC; A : IN STD_LOGIC; B : IN STD_LOGIC; L1 : IN STD_LOGIC; L0 : IN STD_LOGIC; Y : OUT STD_LOGIC ); END mlu; * ARCHITECTURE mlu_dataflow OF mlu IS SIGNAL A1 : STD_LOGIC; SIGNAL B1 : STD_LOGIC; SIGNAL Y1 : STD_LOGIC; SIGNAL MUX_0 : STD_LOGIC; SIGNAL MUX_1 : STD_LOGIC; SIGNAL MUX_2 : STD_LOGIC; SIGNAL MUX_3 : STD_LOGIC; SIGNAL L: STD_LOGIC_VECTOR(1 DOWNTO 0); ? BEGIN A1= NOT A WHEN (NEG_A=1) ELSE A; B1= NOT B WHEN (NEG_B=1) ELSE B; Y = NOT Y1 WHEN (NEG_Y=1) ELSE Y1; MUX_0 = A1 AND B1; MUX_1 = A1 OR B1; MUX_2 = A1 XOR B1; MUX_3 = A1 XNOR B1; L = L1 L0; with (L) select Y1 = MUX_0 WHEN 00, MUX_1 WHEN 01, MUX_2 WHEN 10, MUX_3 WHEN OTHERS; END mlu_dataflow; * TB library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity MLU_TB is end MLU_TB; architecture MLU_TB_ARCHITECTURE of MLU_TB is component mlu port( NEG_A : in std_logic; NEG_B : in std_logic; NEG_Y : in std_logic; A : in std_logic; B : in std_logic; L1 : in std_logic; * L0 : in std_logic; Y : out std_logic ); end component; -- Stimulus signals - signals mapped to the input and inout ports of tested entity signal TEST_NEG_A : std_logic; signal TEST_NEG_B : std_logic; signal TEST_NEG_Y : std_logic; -- Observed signals - signals mapped to the output ports of tested entity signal TEST_Y : std_logic; signal TEST_AB: std_logic_vector(1 downto 0); signal TEST_SEL: std_logic_vector(1 downto 0); * -- Unit Under Test port map Begin UUT : mlu port map ( NEG_A = TEST_NEG_A, NEG_B = TEST_NEG_B, NEG_Y = TEST_NEG_Y, A = TEST_AB(1), B = TEST_AB(0