第7章 VHDL有限状态机设计N.ppt

模块介绍 MAIN模块 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;? entity main is port(clk_in :in std_logic;--1024Hz cnt_en:in std_logic; reset:in std_logic; seg_drive:out std_logic_vector(7 downto 0); bit_drive:out std_logic_vector(3 downto 0) ); end main;? architecture behav of main is? component div port(clk :in std_logic; outy : out std_logic ); end component;? component cnt4 port(clk:in std_logic; date:out std_logic_vector(1 downto 0) ); end component;? component cnt10 port(clk:in std_logic; rst : in std_logic; ena : in std_logic; count : out std_logic; outy : out std_logic_vector(3 downto 0) ); end component;? component bitsel port(b : in std_logic_vector(1 downto 0); bsel: out std_logic_vector(3 downto 0)); end component;? component decl8s port ( a :in std_logic_vector(3 downto 0); led8s : out std_logic_vector(7 downto 0)); end component; ?signal clk1: std_logic; signal out1:std_logic_vector(3 downto 0); signal mux_in:std_logic_vector(1 downto 0); begin u1:div port map(clk=clk_in,outy=clk1); u2:cnt10 port map(clk=clk1,rst=reset,ena=cnt_en,outy=out1,cout=cout); u3:cnt4 port map(clk=clk_in,date=mux_in); u4:bitsel port map(b= mux_in,bsel=bit_drive); u5:decl8s port map(a= out1,led8s=seg_drive);? end behav; 4位10进制计数显示模块 CLK RST ENA 4位10进制计数显示模块 模块介绍 6、MUX41模块 LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY mux41 IS PORT( L0,L1,L2,L3 : IN STD_LOGIC_VECTOR(3 downto 0); DATE : IN STD_LOGIC_VECTOR(1 downto 0); OUTY : OUT STD_LOGIC_VECTOR(3 downto 0)); END mux41; ARCHITECTURE archmux OF mux41 IS BEGIN OUTY=L0 WHEN (DATE=00) ELSE L1 WHEN (DATE=01) ELSE L2 WHEN (DATE=10) ELSE L3 WHEN (DATE=11) ELSE 0000; END archmux; 模块介绍 MAIN模块 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_un