常用基本模块的VERILOG描述概要1.pptVIP

* Table 7.1 Verilog Operators. *Not supported in some Verilog synthesis tools. In the Quartus II tools, multiply , divide, and mod of integer values is supported. Efficient design of multiply or divide hardware may require the user to specify the arithmetic algorithm and design in Verilog. Bitwise Negation ~ Bitwise XOR ^ Bitwise OR | Bitwise AND logical OR || logical AND logical negation ! greater than or equal = greater than less than or equal = less than Inequality != equality = rotate right rotate left Concatenation – used to combine bits { } Modulus* % Division* / Multiplication* * Subtraction - Addition + Operation Verilog Operator module gatenetwork(A, B, C, D, X, Y); input A; input B; input C; input [2:1] D; output X, Y; reg Y; // concurrent assignment statement wire X = A ~(B|C) (D[1] ^ D[2]); /* Always concurrent statement- sequential execution inside */ always @( A or B or C or D) Y = A ~(B|C) (D[1] ^ D[2]); endmodule module DEC_7SEG(Hex_digit, segment_a, segment_b, segment_c, segment_d, segment_e, segment_f, segment_g); input [3:0] Hex_digit; output segment_a, segment_b, segment_c, segment_d; output segment_e, segment_f, segment_g; reg [6:0] segment_data; always @(Hex_digit) /* Case statement implements a logic truth table using gates*/ case (Hex_digit) 4’b 0000: segment_data = 7b 1111110; 4’b 0001: segment_data = 7b 0110000; 4’b 0010: segment_data = 7b 1101101; 4’b 0011: segment_data = 7b 1111001; 4’b 0100: segment_data = 7b 0110011; 4’b 0101: segment_data = 7b 1011011; 4’b 0110: segment_data = 7b 1011111; 4’b 0111: segment_data = 7b 1110000; 4’b 1000: segment_data = 7b 1111111; 4’b 1001: segment_data = 7b 1111011; 4’b 1010: segment_data = 7b 1110111; 4’b 1011: segment_data = 7b 0011111; 4’b 1100: segment_data = 7b 1001110;