第三章_DSP_Builder设计入门.ppt

内容与要点 主要内容： DSP Builder 工具介绍；设计流程；设计规范；模块库；设计实例。 本章要点： DSP Builder 设计流程、规范；Simulink模型仿真；利用MATLAB建模工具和DSP Builder开发环境，认识如何将算法级仿真向硬件模块实现过渡的设计过程。 目录(1) 第一节、 DSP Builder概述 DSP Builder概述 DSP Builder特性 DSP Builder设计流程 DSP Builder软件安装 实例 目录(2) 第二节、 Altera DSP Builder模块库 AltLab库 算术库 总线控制库 复信号处理库 Rate Change模块库 状态机函数库 存储器(Storage）模块库 MegaCore函数支持 其它库 Implementing DSP Designs in FPGA Overview The Programmable Solutions Company? Agenda Overview Designing with DSP Builder Library Blocks Simulating Debugging with DSP Builder Intellectual Property (IP) Implementation FIR, NCO and FFT IP Functions Appendix Introduction to Altera Devices Hardware Acceleration Using Nios II What Is a DSP Processor? Microprocessor With Specialized Instructions Hardware for DSP Applications Optimized For High-Performance, Repetitive and Numerically Intensive Tasks Hardware Fixed Floating Point Multipliers Co-Processors Special Memory Structures Multiple Access Memories For Faster Computations Run Arithmetic Calculations Faster than General Processors What Is an FPGA? Field Programmable Gate Array Device that Has a Regular Architecture (Set of Blocks) that Can Be Programmed for Various Functions “Glue” Logic Customizable Hardware Solution Configurable Processors DSP Processors vs. FPGAs Extending Range of Altera Reconfigurable DSP Solutions FPGA / DSP Challenges Designing With FPGAs Is Different!! Different Set of Tools C-Code vs. VHDL / Verilog System-Level Development Verification Software/Hardware Co-Development Software Design Optimization Addressing Challenges 1) System-level Development Verification DSP Builder Tool System Integration Bit-true Cycle Accurate Models Automatic Translation into Hardware 2) Hardware/Software Integration SOPC Builder Tool Nios? II Processor 3) Design Optimization Hardware Acceleration Flexibility in System Partitioning Implementing DSP Designs in FPGAs Matlab Simulink Overview The Mathworks Headquarters in Natick, near Boston Founded in 1984, Priva