第7章_有限状态机设计与LPM应用研究.ppt

实 验 与 设 计 (6) 实验内容4：在图7-14的电路中在增加一个锯齿波发生器，扫描时钟与地址发生器的时钟一致，即CLK3MHz。锯齿波数据通过另一个D/A输出，控制示波器的X端（不用示波器内的锯齿波信号），而Y端由原来的D/A给出RAM中的采样信息，由此完成一个比较完整的存储示波器的显示控制。 实 验 与 设 计 【例7-17】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ADCINT IS PORT (D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); CLK ,EOC : IN STD_LOGIC; ALE, START, OE, ADDA,LOCK0 : OUT STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END ADCINT; ARCHITECTURE behav OF ADCINT IS TYPE states IS (st0, st1, st2, st3,st4) ; SIGNAL current_state, next_state: states :=st0 ; 接上页 SIGNAL REGL : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL LOCK，START0 : STD_LOGIC; BEGIN ADDA = 1; Q = REGL; LOCK0 = LOCK ; OE=1; COM: PROCESS(current_state,EOC) BEGIN CASE current_state IS WHEN st0=ALE=0;START0=0;LOCK=0; next_state = st1; WHEN st1=ALE=1;START0=1;LOCK=0; next_state = st2; WHEN st2= ALE=0;START0=0;LOCK=0; IF (EOC=1) THEN next_state = st3; ELSE next_state = st2; END IF ; WHEN st3= ALE=0;START0=0;LOCK=0; next_state = st4; WHEN st4= ALE=0;START0=0;LOCK=1; next_state = st0; WHEN OTHERS = next_state = st0; 接上页 END CASE ; END PROCESS COM ; REG: PROCESS (CLK) BEGIN IF (CLKEVENT AND CLK=1) THEN current_state=next_state; END IF; END PROCESS REG ; LATCH1: PROCESS (LOCK) BEGIN IF LOCK=1 AND LOCKEVENT THEN REGL = D ; END IF; END PROCESS LATCH1 ; LK: PROCESS (CLK) BEGIN IF (CLKEVENT AND CLK=1) THEN START=START0 ; END IF; END PROCESS LK ; END behav; 【例7-18】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT9B IS PORT (CLK,CLR : IN STD_LOGIC; FULL : OUT STD_LOGIC; DOUT : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) ); END CNT9B; ARCHITECTURE behav OF CNT9B IS SIGNAL CQI : STD_LOGIC_VECTOR(8 DOWNTO 0); BEG