IC设计模拟的经典的面试题及其答案（IC design simulation of classic interview questions and their answers）.doc

IC设计模拟的经典的面试题及其答案（IC design simulation of classic interview questions and their answers） Latch up is most easily produced in an I/O circuit which is susceptible to external interference and occasionally occurs within the internal circuit Latch up refers to the cmos chip, the power supply power GND VDD and ground (VSS) as a result of the parasitic PNP and NPN bipolar BJT influence each other, resulting in low impedance path, it exists between the VDD gnd causes large current With the development of IC manufacturing process, the density and integration of the packaging become higher and higher, and the possibility of latching up is increasing The excessive amount of electricity generated by Latch up may cause permanent damage to the chip, and Latch up is one of the most important measures of IC Layout Q1 is a vertical PNP BJT, and base is nwell, and the gain of base to collector (collector) can be hundreds of times. Q2 is a side-type NPN BJT, the base is P substrate, and the gain of the collector can be tens of times. Rwell is the parasitic resistance of nwell; The Rsub is the substrate resistance. More than four elements constitute a silicon controlled rectifier (SCR) circuit, when no interference was not triggered by two BJT, collector current is C - B reverse leakage current, current gain is very small, the Latch up wont produce. When one of the BJTs collector current is exposed When a disturbance is suddenly increased to a certain value, it will be fed back to another BJT, thus causing two BJTS to be triggered by the trigger, VDD to GND (VSS) It forms a low resistance pathway and the Latch up is created. The specific cause of Latch up ? The change of VDD at the beginning of the chip results in sufficient current in the parasitic capacitance between nwell and P substrate. When the VDD rate is large enough, it will cause Latch up. ? When the signal change of I/O exceeds the range of vdd-gnd (VSS), there is a large current generated in the chip, which can also trigg