Verilog12题库.pptVIP

Verilog 分频稳定数码管 always @ (posedge clk) begin if(counter== 0) begin counter = COUNT1; clk_500Hz = ~clk_500Hz; end else counter = counter-1; end 数码管显示商品价格 /*分频后将时钟给数码管，数码管分别显示放入钱的多少、商品价格*/ always @(posedge clk_500Hz) begin case(flag) 2b00: begin dis_mony = {4b1110,led7(price_all%10),1b1}; dis_price = {4b1110,led7(price%10),1b1}; flag = 2b01; end 2b01: begin dis_mony = {4b1101,led7(price_all/10),1b0}; dis_price = {4b1101,led7(price/10),1b0}; flag = 2b00; end endcase end 数码管显示函数 function [6:0] led7; input [3:0] dis_input; begin case (dis_input) 0 : led7 = ~7b111_1110; 1 : led7 = ~7b011_0000; 2 : led7 = ~7b110_1101; 3 : led7 = ~7b111_1001; 4 : led7 = ~7b011_0011; 5 : led7 = ~7b101_1011; 6 : led7 = ~7b101_1111; 7 : led7 = ~7b111_0000; 8 : led7 = ~7b111_1111; 9 : led7 = ~7b111_0011; default : led7 = ~7b111_1111; endcase end endfunction endmodule 初始状态 always @(negedge rst or posedge clk) begin if(!rst) begin led = 4b0000;//LED灭 price_all = 0;//价格清零 led_warn = 0; price = 0; beep = 0; end else 投币和商品价钱 case(btn_mon) 3b001:begin price_all = 5;end 3b010:begin price_all = 10;end 3b100:begin price_all = 50;end 3b011:begin price_all = 15;end 3b101:begin price_all = 55;end 3b110:begin price_all = 60;end 3b111:begin price_all = 65;end default:begin price_all = 0;end endcase case(btn_sell) 4b0001:begin price = 5; end 4b0010:begin price = 10; end 4b0100:begin price = 15; end 4b1000:begin price = 20; end default:begin price = 0; end endcase 投币与商品价钱比较 if(btn_ok == 1) begin if(price_all price) //放入钱不足 begin led_warn = 1; price = 0; end else begin //金钱足够 price_all = price_all-price; beep = 1; case(price) //LED灯显示货物卖出 5: begin led = 4b0001;end 10:begin led = 4b0010;end 15: