IC FLOW（集成电路流）.docVIP

IC FLOW（集成电路流） Tutorial -- IC design flow and tools Various manufacturers have their own design process based on the tool of IC, cadence and Synopsys from front to back to the tools, they also have their own IC tools. For example, the IC610 platform, the virtuoso platform, the encounter platform. IC610 integrates cadence Allegro 16 on the basis of IC5141. The software package consists of the following parts: cadence Allegro 16 ic5141 design environment, design environment and Dracula verification tools, Assura verification tools, ic610 design environment (Virtuoso_Layout_Suite_L, ***_XL, ***_GXL) and other tools. Mentor is not clear. Feel cadence in analog, back-end strong, Synopsys in integrated, front-end strong. Specific also unclear, wrong, please correct me. Try one, such as cadence: IUS + Novas, Verdi +, SOCE, RTL, Compiler +, LEC+, SOCE +, IC6XX +, Cadence, EXT +, MMSIM + Assura Design flow based on Synopsys tool Source Code Verilog/VHDL Design specification check LEDA Simulation VCS, Scirocco Automatic generation of test platform and vector VERA PhysicalCompiler, ClockTreeCompiler (0.18um) DC-Expert, DC-Ultra (0.180.35um) Design of testability DFTCompiler Low power design PowerCompiler FPGA synthesis FPGA Compiler II Static timing analysis PrimeTime Formal verification Formality Layout of Astro (0.18um) Apollo (0.180.35um) Power dissipation and electrical drift, Crosstalk analysis, optimization, Mars-Rail, Mars-Xtalk Logical diagram / layout CosmosSE/CosmosLE LVS, DRC, Hercules Circuit simulation, NanoSim (ST-SimXT), high speed, large-scale ST-Hspice high precision Extraction of interconnect parameters ST-RCXT A back-end process: 1. Prepare data. 2, FloorPlanning with Encounter 3, Placement with ICC 4, CTS with Encounter 5, CTS after the optimization to ICC. 6, Routing-- Encounter 7, Routing after the Timing optimization to ICC. After that, use Encounter ReRoute. Total flow: 1 structural and electrical regulations. 2RTL level code design and simulation test