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Combining Branch Predictors
Scott McFarling
June 1993
d i g i t a l Western Research Laboratory 250 University Avenue Palo Alto, California 94301 USA
Abstract
One of the key factors determining computer performance is the degree to
which the implementation can take advantage of instruction-level paral-
lelism. Perhaps the most critical limit to this parallelism is the presence of
conditional branches that determine which instructions need to be executed
next. To increase parallelism, several authors have suggested ways of
predicting the direction of conditional branches with hardware that uses the
history of previous branches. The different proposed predictors take advan-
tage of different observed patterns in branch behavior. This paper presents
a method of combining the advantages of these different types of predictors.
The new method uses a history mechanism to keep track of which predictor
is most accurate for each branch so that the most accurate predictor can be
used. In addition, this paper describes a method of increasing the usefulness
of branch history by hashing it together with the branch address. Together,
these new techniques are shown to outperform previously known approaches
both in terms of maximum prediction accuracy and the prediction accuracy
for a given predictor size. Specifically, prediction accuracy reaches 98.1%
correct versus 97.1% correct for the most accurate previously known ap-
proach. Also, this new approach is typically at least a factor of two smaller
than other schemes for a given prediction accuracy. Finally, this new ap-
proach allows predictors with a single level of history array access to outper-
form schemes with multiple level
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