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announcements - university of california, berkeley(公告u2014u2014加州大学伯克利分校)
EE290C - Spring 2004
Advanced Topics in Circuit Design
High-Speed Electrical Interfaces
Lecture 8
Components
Phase-Locked Loops
Borivoje Nikolic
February 12, 2004
Announcements
Homework #1 due today
ISSCC next week
No classes Tu and Th
Sign up for paper review by Friday
Presentations the week after ISSCC
2
1
Outline
Ethernet transmitters
Timing issues
DLL/PLL properties
Loop components
3
100Base-T Transmitters
Specification:
4ns±1ns rise time with 8ns 3-level (MLT-3) symbols (4/5
enoding)
Limits the EMI from the connector/cable
5% amplitude tolerance with 2% matching of +1 and -1 levels
4
2
100Base-T Transmitters
Biasing techniques to guarantee slopes over PVT
D. Nack, K. Dyer, VLSI’00
Everitt, JSSC 12/98
5
PLLs and DLLs
Material:
Razavi, Monolitic Phase-Locked Loops and Clock
Recovery Circuits, IEEE Press 1996
Maneatis, VLSI Circuits Tutorial, 1996
Razavi, VLSI Circuits Tutorial, 2000
6
3
Clocking : Terminology
Can do with or
without CDR
Needs CDR!
7
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