Lecture 7 静态时序分析.pdfVIP

《集成电路设计》 第七讲静态时序分析 孟令国 myyanghua@163.com 山东大学 物理学院 Static Timing Analyzer Using PrimeTime Dec 23 2007 Presented by zhao icdesign_zhao@126.com 2013-2-21 2 Agenda Basic Flow Advanced Analysis Summary Example 2013-2-21 3 STA instruction Static timing analysis concept Verifies timing (setup, hold …) Is exhaustive Uses formal, mathematical techniques instead of vectors Does not use dynamic logic simulation STA : Easier, faster debugging of your design timing 2013-2-21 4 Comprehensive Timing Checks Many types of timing and design rule checks Timing checks can be delay calculated or SDF annotated Setup and hold check Design rule checks consistent with DC, PC, Astro 2013-2-21 5 Basic Timing Analysis Flow Using PrimeTime Setup Design Environment Search path, link path Read designs, libraries, then link Read sdf and set operation condition, environment setting Specify Timing Assertions Clock period/waveform/uncertainty/latency Input/output delays Specify Timing Exceptions Multi-cycle paths and False paths Min/max delays, segmentation, disabled arcs Perform Analysis, Create Reports Check timing Timing reports and constraint reports Bottleneck and coverage analysis reports 2013-2-21 6 Set Up Environment Definitions search_path: specifies where to search for design and library data link_path: specifies which design and library d