曼切斯特大学《Electronic Circuit Design》Lecture 09.pdfVIP

Lecture 9: DDDaaatttaaa AAAcccqqquuuiiisssiiitttiiiooonnn SSSyyysssttteeemmmsss::: AAAnnnaaallloooggg tttooo DDDiiigggiiitttaaalll CCCooonnnvvveeerrrsssiiiooonnn van Silfhout EE4 101 1 A na log-to-dig ita l c o nv e rte rs Single slope or ramp Successive approximation Dual slope Parallel or f lash 7 van Silfhout EE4101 - Lecture 9 2 S ing le s lo pe o r ra mp A DC Composed of three basic elements A binary counter A digital-to-analog converter An analog comparator Operation Counter is reset Analog input is sampled While V V counter increments A B When V =V counter stops and binary code is available at the output A B Characteristics N Relatively slow since conversion time could be up to 2 , where N is the resolution of the ADC 8 van Silfhout EE4101 - Lecture 9 3 B a s ic S /H c irc uit Basic elements Voltage followers FET switch Operation IC1 provides low Zout version of input signal Q1 passes the signal during sample and disconnects during hold C preserves the value during hold IC2 is a high Zin op-amp to minimize capacitor discharge during hold van Silfhout EE4101 - Lecture 9