DDR3与DDR2的不同之处(DDR3 is different from DDR2).docVIP

DDR3与DDR2的不同之处(DDR3 is different from DDR2).doc

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DDR3与DDR2的不同之处(DDR3 is different from DDR2)

DDR3与DDR2的不同之处(DDR3 is different from DDR2) DDR3 is different from DDR2 1. Number of logical Bank The DDR2 SDRAM has 4Bank and 8Bank designs designed to meet the needs of future large-capacity chips. DDR3 is likely to start at 2Gb, so the starting logic Bank is 8, and it is ready for the next 16 logical Bank. 2. Package (Packages) DDR3 has added some new features, so it will increase in the pins, 8bit chip with 78 ball FBGA package, 16bit chip with 96 ball FBGA package, and DDR2 with 60/68/84 ball FBGA to encapsulate three specifications. And DDR3 must be green to contain any harmful substances. 3. Burst Length (BL, Burst Length) Because DDR3 prefetching is 8 bit, so sudden transfer cycle (BL, Burst Length) is also fixed of 8, for DDR2 and early DDR architecture system, BL = 4 also is commonly used, DDR3 4 - bit for this added a Burst Chop (sudden mutation) model, which consists of a BL = 4 read operations with a write operation for synthesis of BL = 4 a BL = 8 data Burst transmission, will be able through A12 address line to control the emergency mode. It should also be noted that any interruption operation will be banned in DDR3 memory and will not be supported, instead, more flexible emergency transfer control (such as a 4bit order burst) will be replaced. 3. Timing (Timing) Just as DDR2 changes from DDR to delayed cycle count, DDR3s CL cycle will also be higher than DDR2. DDR2s CL range is generally between 2 and 5, while DDR3 is between 5 and 11, and the design of additional delay (AL) changes. At DDR2, the range of AL is 0 to 4, while at DDR3, AL has three options: 0, cl-1 and cl-2 respectively. In addition, DDR3 adds a new sequential parameter, the write delay (CWD), which is determined based on the specific work frequency. New features - Reset (Reset) Reset is an important addition to DDR3, and a pin is prepared for this. DRAM has long demanded that this feature be added, and is now finally being implemented on DDR3. This pin will make the initialization of

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