EDA题库的.doc

英文缩写与全称： 1 EDA Electronic Design Automation 2 GAL Generic Array Logic 3 CPLD Complex Programmable Logic Device 4 FPGA Field Programmable Gate Array 5 EAB embedding array block 6 SOPC system on a programmable chip 7 VHDL Very-high-speed Integrated Circuit Hardware Description Language 8 IEEE The institute of Electrical and Electronics Engineers 9 ISP In-System Programmability 10 PAC Programmable Analog Circuits 11 HDL Hardware Description Language 12 SOC system on a chip 13 OLMC Output Logic Macro Cell 14 ASIC Application Specific Integrated Circuits 15 JTAG Joint Test Action Group 16 LUT Look Up Table 17 BST Board Scan Test 18 ICR In Circuit Reconfigurability 19 LE Logic Element 20 EEPROM Electrically Erasable Programmable Read Only Memory 21 SRAM Static Random Access Memory 22 LAB Logic Array Block 23 PROM Programmable Read Only Memory 24 IC Integrated Circuit 25 EAB embedding array block 26 IP Intellectual Property 27 PLA Programmable Logic Array 28 GRP Global Routing Pool 29 PIA Programmable Interconnect Array 指出下列程序设计元件的中文名，指出语法错误并改正，给出改正后的时序图： 1、 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; 　USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4B IS PORT (CLK，RST，ENA: IN STD_LOGIC;OUTY : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT : OUT STD_LOGIC ); END CNT4B; ARCHITECTURE behav OF CNT4B IS SIGNAL CQI : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(CLK, RST, ENA) BEGIN IF RST = 1 THEN CQI = 0000;　　　　　　　0000ELSIF CLKEVENT AND CLK = 1 THEN IF ENA = 1 THEN CQI = CQI + 1;　　　　　　　1ELSE CQI = 0000;END IF;　　　　　　　　　　　　　　　　　　　　　END IF;OUTY = CQI ;END PROCESS; COUT=CQI(0) AND CQI(1) AND CQI(2) AND CQI(3); END behav; 含异步清0和同步时钟使能的4位加法计数器 ２、 LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ADDER8 IS PORT ( CIN : IN STD_LOGIC; A, B : IN STD_LOGIC_VECTOR(7 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); COUT : OUT STD_LOGIC_VECTOR ); END ADDER8; ARCHITECTURE behav OF ADDER8 IS SIGNAL SINT : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); BEGIN