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多核处理器片上存储系统研究
36 4 2010 2
Vol.36 No.4 Computer Engineering February 2010
·· 2010 A TP333
( 410073)
cache cache
cache
cache
Research on On-chip Memory System of Multi-core Processor
HUANG An-wen, GAO Jun, ZHANG Min-xuan
(National Key Laboratory for Parallel and Distributed Processing, School of Computer Science,
National University of Defense Technology, Changsha 410073)
AbstractAiming at the problem that memory system on chip becomes a bottleneck of improving the performance of multi-core processor as the
speed distinction between CPU and memory increases. This paper analyses the design characters of memory system in multi-core processor, such as
Non-Uniform Cache Access(NUCA) caused by delay, constraint to access performance of connection between core and cache, and complexity of
on-chip cache design.
Key wordsmulti-core; memory system; Non-Uniform Cache Access(NUCA)
1 T1 T2 ROCK Sun
IBM, Intel, AMD Fujitsu
Web
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3.1 UltraSPARC T2 ROCK
Sun UltraSPARC T2[3]5.7 KB
0.3 KB
16 KB cache 8 KB cache
2 4 MB L2-cache8 Bank 16
L2-cache 9
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