t pN 最小尺寸反相器C g1.PPT

Buffer Design 1 1 1 1 8 64 64 64 64 4 2.8 8 16 22.6 N f tp 1 64 65 2 8 18 3 4 15 4 2.8 15.3 例5.8 引入缓冲器级的影响 无缓冲器的设计、两级缓冲器以及优化的反相器链对于不同F值所对应的tp,opt/tp0值（γ=1） 驱动较大负载时，采用反相器链可达到明显加速效果 5.15 确定反相器链尺寸 a. 为通过一最小尺寸反相器（Ci=10fF）驱动一大电容（CL=20pF），引入两级缓冲器，如图5.12所示。设最小尺寸反相器传输延时为70ps，且逻辑门的输入电容与其尺寸成正比。确定两级缓冲器的尺寸及反相器链最小延时。 b. 如可以加入任意多级反相器使延时最小，应加入几级？具体延时数值为多少（考虑自载效应）？ c. 解释方案a和方案b的优缺点 5.5 Power Dissipation Where Does Power Go in CMOS? 5.5.1 Dynamic Power Dissipation Energy/transition Power = Energy/transition * f = C L * V dd 2 * f Vin Vout C L Vdd Need to reduce C L , V dd , and f to reduce power. Not a function of transistor sizes! 电容引起的功耗 after 0-1 power distribution: Half of the power consumed on PMOS! But no matter charging or discharging, it has no relation to size! A. Node Transition Activity and Power Example: Power Consumption For a CMOS chip with 0.25um technology, clock frequency is 500MHz, per load is about 15fF/gate, if fout=4, for VDD=2.5V: p=50uw/gate if there are 1 million gates on the chip, and on each clock edge, there is an upturn, the whole power is 50W!! Example 5.11 5.12 B. Transistor Sizing for Minimum Energy Reducing VDD can low down power consumption, for example, when VDD reduced from 2.5V to 1.25V, power consumption could decrease from 5W to 1.25W. But when VDD close to 2VT, performance would decrease evidently! 当电源电压的下限取决于外部限制或者当减小电源电压引起的性能降低不能被接受时，减少功耗的唯一方法就是减少等效电容： 实际电容和翻转活动性 减少翻转活动性只能在逻辑和结构的抽象层次上实现。由于在一个组合逻辑电路中大部分的电容是晶体管电容（栅电容和扩散电容），因此在低功耗设计时保持这部分最小是有意义的 Transistor Sizing for Minimum Energy Goal: Minimize Energy of whole circuit Find parameters: f (size coefficient) and VDD tp ? tpref (circuit with f=1 and VDD =Vref) A CMOS inverter which was driven by a minimum inverter has a load of Cext Transistor Sizing Performance Constraint (g=1: intrinsic cap Cint equals to gate cap Cg, f=1) …(1) 1式建立了f与电源电压之间的关系，下图画出了对于不同F时的关系。这些曲线都有一个明显的最小值。由最小尺寸起增加反相器的尺寸最初会使性能提高，因此允许降低电源电压。这在达到最优尺寸系数前一直都是有效的。进一步加大器件尺寸只会