Coding And Scripting Techniques For FSM （编码和脚本技术FSM）.pdf

Coding And Scripting Techniques For FSM Designs With Synthesis-Optimized, Glitch-Free Outputs SNUG-2000 Boston, MA Clifford E. Cummings Voted Best Paper 2nd Place Sunburst Design, Inc. ABSTRACT A common synthesis recommendation is to code modules with a cloud of combinational logic on the module inputs and registered logic on all of the module outputs. FSM designs often include outputs generated from combinational logic based on the present state or combinational Mealy outputs. This paper details design and synthesis techniques that support the coding and synthesis scripting of glitch-free registered outputs for Finite State Machine designs. 1.0 Introduction Efficient state machine design using a Hardware Description Language (HDL), such as Verilog, can take many forms [1][2]. Are there specific forms that lend themselves well to synthesis? This paper describes some common coding styles and highlights two coding styles with registered outputs that are well suited for commonly used synthesis techniques. This paper will briefly describe coding styles that generate combinational logic outputs and then will detail coding styles that generate registered outputs and describe why the registered output coding styles are often beneficial to synthesis strategies. 2.0 Basic FSM Structure A typical block diagram for a Finite State Machine (FSM) is shown in Figure 1. inputs (Mealy State Machine Only) combinational sequential combinational logic