veriog+任意波形发生器程序.docVIP

module fen_10 (fclk,clk,reset); //10分频模块 output fclk; input clk; input reset; reg[2:0] fout; reg fclk; //用always语句，输出为reg型； always @ (posedge clk or posedge reset ) //异步复位； begin if(reset) begin fout=3b0; fclk=0; //实现清零输出； end else if(fout==3b100) begin fout=3b0; fclk=!fclk;// 复位信号为零时，计数值每从0-4，则让新时钟跳变一次，这样原时钟的10个周期内就只有一个新的上升沿； end else fout=fout+1; end endmodule module add_ram (dout,fclk,data,rb); //波形存储器模块 output[7:0] dout; input fclk; input[2:0] data; input rb; wire fclk,rb; wire[7:0] dout; reg[10:0] din; assign dout[7:0]=din[10:3];// 取新地址的前八位； always @ (posedge fclk or posedge rb)// 用新的时钟信号作为累加模块的时钟信号; begin if(rb) din=11b0; //实现清零输出； else din[10:0]=din[10:0]+ data[2:0]; // 当上升沿带到来时，让原11位地址在地址加法器内与一个输入变量data进行一次相加，得到新的11位地址； end endmodule module sin(rout,dout,en,fclk); //正弦波形输出模块 input[7:0] dout; input en,fclk; output[7:0] rout; wire[7:0] dout; wire en,fclk; reg[7:0] rout; always @(posedge fclk or posedge en) begin if(en) rout=8h00; else begin case(dout) //在正弦波形输出表中查找相应的值进行输出; 8h0:rout=8h7f; 8h1:rout=8h82; 8h2:rout=8h85; 8h3:rout=8h88; 8h4:rout=8h8b; 8h5:rout=8h8e; 8h6:rout=8h91; 8h7:rout=8h94; 8h8:rout=8h97; 8h9:rout=8h9a; 8ha:rout=8h9d; 8hb:rout=8ha0; 8hc:rout=8ha3; 8hd:rout=8ha6; 8he:rout=8ha9; 8hf:rout=8hac; 8h10:rout=8haf; 8h11:rout=8hb2; 8h12:rout=8hb5; 8h13:rout=8hb8; 8h14:rout=8hba; 8h15:rout=8hbd; 8h16:rout=8hc0; 8h17:rout=8hc2; 8h18:rout=8hc5; 8h19:rout=8hc8; 8h1a:rout=8hca; 8h1b:rout=8hcd; 8h1c:rout=8hcf; 8h1d:rout=8hd1; 8h1e:rout=8hd4; 8h1f:rout=8hd6; 8h20:rout=8hd8; 8h21:rout=8hda; 8h22:rout=8hdd; 8h23:rout=8hdf; 8h24:rout=8he1; 8h25:rout=8he3; 8h26:rout=8he4; 8h27:rout=8he6; 8h28:rout=8he8; 8h29:rout=8hea; 8h2a:rout=8heb; 8h2b:rout=8hed; 8h2c:rout=8hee; 8h2d:rout=8hf0; 8h2e:rout=8hf1; 8h2f:rout=8hf3; 8h30:rout=8hf4; 8h31:rout=8hf5; 8h32:rout=8hf6; 8h33:rout=8hf7; 8h34:rout=8hf8; 8h35:rout=8hf9; 8h36:rout=8hfa; 8h37:rout=8hfa; 8h38:rout=8hfb; 8h39:rout=8hfc; 8h3a