DSP 28335 教程 7课件.pptVIP

Analog-to-Digital Converter;Learning Objectives;ADC Module Block Diagram (Cascaded Mode);ADC Module Block Diagram (Dual-Sequencer mode);ADC Operating Mode Choices;ADC Clocking Flow;Analog-to-Digital Converter RegistersAdcRegs.register (lab file: Adc.c);ADC Control Register 1AdcRegs.ADCTRL1;ADC Control Register 1AdcRegs.ADCTRL1;ADC Control Register 2AdcRegs.ADCTRL2;ADC Control Register 2AdcRegs.ADCTRL2;ADC Control Register 3AdcRegs.ADCTRL3;Maximum Conversion Channels RegisterAdcRegs.ADCMAXCONV;ADC Input Channel Select Sequencing Control RegistersAdcRegs.ADCCHSELSEQx;Example - Sequencer Configuration (1 of 2);Example - Sequencer Configuration (2 of 2);ADC Conversion Result Registers;How Can We Handle Signed Input Voltages?;Built-In ADC Calibration;If the offset and gain errors in the datasheet * are unacceptable for your application, or you want to also compensate for board level errors (e.g., sensor or amplifier offset), you can manually calibrate Offset error Compensated in analog with the ADCOFFTRIM register No reduction in full-scale range Ground an input pin, set ADCOFFTRIM to maximum offset error, and take a reading Re-adjust ADCOFFTRIM to make result zero Gain error Compensated in software Some loss in full-scale range Requires use of a second ADC input pin and an upper-range reference voltage on that pin; see “TMS320280x and TMS320F2801x ADC Calibration” appnote #SPRAAD8 for more information Tip: To minimize mux-to-mux variation effects, put your most critical signals on a single mux and use that mux for calibration inputs;ADC Reference SelectionAdcRegs.ADCREFSEL;Lab 6: ADC Sampling;Lab 6: Code Flow Diagram;ti