第10章 VHDL基本语句课件.ppt

10.1 顺序语句 10.2 VHDL并行语句 10.3 属性描述与定义语句;10.1 顺序语句;一、赋值语句;选择值[ | 选择值];ENTITY mux41 IS PORT ( s4 , s3 , s2 , s1 : IN STD_LOGIC ; z4 , z3 , z2 , z1 : OUT STD_LOGIC ) ; END mux41 ;; z1= ‘ 0 ’ ; z2= ‘ 0 ‘ ; z3= ‘ 0 ’ ; z4= ‘ 0 ’ ; - -输入初始值 CASE sel IS WHEN 0 = z1 = ‘1’ ; - -当sel=0 时选中 WHEN 1|3 = z2 = ‘1’ ; - -当 sel为1或3时选中 WHEN 4 To 7 | 2 = z3= ‘1’ ; - -当 sel为2、4、5、6或7时选中 WHEN OTHERS = z4 = ‘1’ ; - -当sel为8~15中任一值时选中 END CASE ; END PROCESS ; END activ ;;CASE value IS WHEN 0 = out = ‘1 ’ ; - - value2~15的值未包括进去 WHEN 1 = out = ‘ 0 ’ ; END CASE . . . CASE value IS WHEN 0 TO 10 = out 1= ‘ 1 ’ ; - -选择值中5~10的值有重叠 WHEN 5 TO 15 = out 1= ‘ 0 ’ ; END CASE ; ;ENTITY alu IS PORT ( a , b : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ; opcode : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ; result : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ); END alu ;; IF ( a = b ) THEN result = x “01” ; ELSE result = x “00” ; END IF ; WHEN not_equal = - - a 、b不相等 IF ( a /= b ) THEN result = x “01” ; ELSE result = x”00” ; END IF ; END CASE ; END PROCESS ; END behave ; ;L 2 : LOOP a := a +1 ; EXIT L 2 WHEN a 10 ; END LOOP L2 ; - -当a大于10时跳出循环 . . . ;ARCHITECTURE opt OF p_check IS SIGNAL tmp : STD_LOGIC ; BEGIN PROCESS (a ) BEGIN tmp = ‘0 ’ ; FOR n IN 0 TO 7 LOOP tmp = tmp XOR a (n) ; END LOOP ; Y = tmp ; END PROCESS ; END opt ;;五、NEXT语句; . . . L_x : FOR cnt_value IN 1 TO 8 LOOP s1 ： a ( cnt_value ) := ‘0’ ;