目的使学生了解CRC原理，并用FPGA验证其功能.ppt

經由Jumper 的Short, clock 輸入的Port 就有許多不同的組合與選擇, 例如: cka 可 驅動gck0, gck1 或gck2; 下表列出每個clock source ckn 所能驅動的gck list Forth 指令800 ckaf :設定cka 為頻率800KHz Programming Frequency Project-1 8-bit Full Adder Design 目的: 了解基本加法器設計 由實例學習FPGA軟体使用 3. 實際下載電路至發展系統, 作即時驗証 儀器及設備: 個人電腦, FPGA發展系統及模擬軟体 First design 1-bit full adder Design 8-bit adder using 1-bit adder 1-bit adder : S=a?b ?ci Cout=a b+b cin+a cin 原理: Simulations 8-bit full adder using 1-bit adder symbol 層次設計 Pin Assignment Input output 用發展系統驗証結果 實例設計2-VGA 顯示控制器 目的: 了解-VGA 顯示控制原理 由實例學習用FPGA作顯示控制 3. 訓練除錯之作即時驗証技術 儀器及設備: 個人電腦, FPGA發展系統發展系統及模擬軟体 1.80MHz 24 bits True Color VGA Interface 2. 8 bits x 3 LED / 8 bits DIP Switch 3. Character/Graphic LCD Module Connector VGA Module 原理 A VGA video signal contains 5 active signals 1.Two signals for synchronization of the video ? Horizontal sync ? Vertical sync 0.7 to 1.0-Volt peak-to-peak level 2. Three color signals ? Red ? Greed ? Blue Video Display Technology (2/2) To reduce flicker due to interference from fluorescent lighting source : ? Refresh rates higher than 60Hz are sometimes used in PC monitors. ? In 320 x 480-pixel model, a 60Hz refresh rate means approximately 80ns duration per pixel. ? A 12.5MHz clock has a period of80ns, which is preferably adopted as the system clock VGA display connector VGA Design Spec 640 pixels X 480-lines H- Sync. freq. = 31.4kHz V- Sync. freq. = 60Hz (60 frame/Sec) Base time = 40ns (25MHz) clock period Display: Show your name in TOP Draw circle radius=1 to 10 changed per second D/A Converter From FPGA To VGA The analog RGB outputs IOR, IOG, and IOB related to the digital inputs are stable : after the clock edge with a two-cycles latency. 方法-配置在發展糸統位置 LED vg7~vg0, vb7~vb0: These groups of LEDs share the ports (connecting to the FPGA) with that of the VGA DAC. The buffers driving these LEDs are turned off by default. 接著建立Constraints File 以指定Pin Assignments to FPGA chip; 2. 點右鍵在Project Icon 選擇New Source