IP核(LPM模块)的EDA软件应用.docVIP

班级：10集成、姓名：崔冰、学号：1015251005 实验四、IP核（LPM模块）的EDA软件应用 工作原理： 正弦波信号发生器的结构由4部分组成：计数器或地址发生器（6位）；正弦信号数据ROM（6位地址线，8位数据线），含有64个8位数据VHDL顶层设计；8位D/A。 顶层文件Singt。Vhdl在FPGA中实现，包含两个部分：ROM的地址发生器，由6位计数器担任；正弦数据ROM，由LPM ROM模块构成；LPM_ROM底层是FPGA中的EAB或M9K等模块。地址发生器的时钟CLK的输入频率f0下每周期的波型数据点数，以及D/A输出的频率f的关系是：f=f0/64。 定制初始化数据文件： 使用mif型或hex型，例如： 定制ROM： -- megafunction wizard: %ROM: 1-PORT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: ROM.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 7.2 Build 151 09/26/2007 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2007 Altera Corporation --Your use of Altera Corporations design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY ROM IS PORT ( address : IN STD_LOGIC_VECTOR (5 DOWNTO 0); clock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END ROM; ARCHITECTURE SYN OF rom IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONEN