电子科技大学 电子设计和自动第四讲.pptVIP

电子设计自动化技术 第四讲VHDL的主要描述语句;本章要点;VHDL主要描述语句分类;VHDL描述语句;VHDL主要描述语句分类;VHDL主要描述语句分类;VHDL主要描述语句分类;VHDL主要描述语句分类;描述功能的语句;对象的赋值;VHDL描述语句;;Concurrent Assignment Statement;Entity test1 Is Port ( a, b : in std_logic; c, d : out std_logic); end test1; architecture test1_a of test1 is begin c = a and b; d = a or b; end test1_a;;C = AB;Concurrent StatementsforCombinational Logic;Concurrent Statements;Putting them all together;(1) Simple Signal Assignment ;What kind of logic support;We want 5 Inputs AND-Gate;(2) Conditional Signal Assignments;If we want more -- 4 to 1 Mux;(3) Select Signal Assignments;If I want more choice ---;Review;作 业;作 业;VHDL描述语句;PROCESS语句一般格式 ;Process Statement;Entity test1 is Port ( clk, d1, d2 : in std_logic; q1, q2 : out std_logic); end test1; architecture test1_body of test1 is begin Process (clk, d2) begin if (clk’event and clk = ‘1’) then q2 = d2; end if; end process; Process (clk, d1) begin if (clk’event and clk= ‘1’) then q1 = d1; end if; end process; end test1_body;;The two processes execute in parallel;Now, we know what is concurrent statement process statement Q : What is the usage of this in VHDL ? A : Engineer can use the mixture of concurrent statement and process statement to do the design;How to ... ?