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一种无乘法器的小功率pfc芯片电路设计_51_55
一种无乘法器的小功率pfc芯片电路设计_51_55
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Design and simulation results of the fourth chapter of XW8201 system
Forty-three
The expression is as follows:
R2 = RT (1 + 0 A (T T0))
The expression into above Vbe and R2, Iref expression:
Iref = D3 (VBE + 0 B (T T0) 0 (1) RT + A (T T0))
(3-43)
(3-44)
Here, we hope
Iref T
= 0
Iref ART 0VBE 0 + ABRT 0 (T T0) ART 0 D3 BRT 0 ABRT 0 (T T0) (3-45a) T (RT = 0 (1 + A (T T0) 2)
RT = 0 (AV BE 0 AD 3 B (RT) 0 (1 + A (T T0) = A (V) 2 BE 0 D 3 RT 0 (1) B + A (T T0) 2)
(3-45b)
Ignore the two order effect under the condition of the A, B as a constant, if the first Iref is determined, using the above expression, R2 and Vref. can be determined according to the bias circuit to provide the chip area and power consumption, comprehensive consideration, take Iref=24uA. through temperature compensation, simulation output current Iref current source bias circuit the results shown in Figure 3.20, the temperature from -40 to 125 DEG C., current change 10nA.
Figure 3.20 reference current temperature compensation
Figure 3.21 is the simulation waveform variation of the reference current with the resistance process, solve this problem by using trimming technology in the design, not detail here after.Trimming current can be done within an error of 8%.
Forty-four
A design of Multiplierless PFC chip circuit
In Figure 3.21 the reference current temperature, simulation waveform of resistance change
Optimization of 3.3.5THD circuit
1) function
To understand the causes of [34,35] THD optimization, we must first introduce the working process of the zero current detection circuit, zero current detection circuit is chip inductor current zero crossing detection circuit is simple. When detecting the zero current detection circuit to the inductor current drops to zero, outputs a control signal, o
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