vhdl语言设计的电子琴.docVIP

entity dzq is Port ( mid : in STD_LOGIC; low: in STD_LOGIC; hig : in STD_LOGIC; auto : in STD_LOGIC; clk : in STD_LOGIC; LCD: out STD_LOGIC_VECTOR (7 downto 0); index: in STD_LOGIC_VECTOR (7 downto 0); code: out STD_LOGIC_VECTOR (7 downto 0); dout : out STD_LOGIC); end dzq; architecture dzq1 of dzq is signal yd:STD_LOGIC_VECTOR (2 downto 0); signal count0:STD_LOGIC_VECTOR (5 downto 0); signal count:STD_LOGIC_VECTOR (24 downto 0); signal clk2:STD_LOGIC; signal clk1:STD_LOGIC; signal hig2,hig3:STD_LOGIC; signal mid2,mid3:STD_LOGIC; signal low2,low3:STD_LOGIC; signal preclk:STD_LOGIC; signal fout :STD_LOGIC; signal count13:STD_LOGIC_VECTOR (12 downto 0); signal mid4,low4,hig4: STD_LOGIC; signal tone1 : STD_LOGIC_VECTOR (12 downto 0); signal tone0 : STD_LOGIC_VECTOR (12 downto 0); signal index0 : STD_LOGIC_VECTOR (7 downto 0); signal index1 : STD_LOGIC_VECTOR (7 downto 0); begin FP:process(clk,auto) begin if(auto=1) then count=0000000000000000000000000; elsif(clkevent and clk=1) then count=count+1; if(count=101111111111111111111111) then clk2=1; count=0000000000000000000000000; else clk2=0; end if; end if; end process; JISHU:process(clk2) begin if(clk2event and clk2=1) then if(count0=101001) then count0=000000; else count0=count0+1; end if; end if; end process; MUSIC:process(count0,auto,index0) begin if(auto=0) then case count0 is when000000=index0LCD --1 when000001=index0LCD --1 when000010=index0LCD --5 when000011=index0LCD --5 when000100=index0LCD --6 when000101=index0LCD --6 when000110=index0LCD --5 when000111=index0LCD --5 when001000=index0LCD --4 when001001=index0LCD --4 when001010=index0LCD