处理器主要记忆体.ppt

第五章 Memory system Basic Computer Organization Revisited Access time vs cycle time Memory access time A measurement of single access Memory cycle time A measurement of how quickly two back-to-back accesses of a memory chip can be made Cycle time access time due to latency between successive memory accesses DRAM (For construct Main memory) access time - 50 to 150 nanoseconds require a pause (refresh) between back-to-back accesses SRAM (For construct Cache memory) access time - 10 nanoseconds no pause between back-to-back accesses SRAM SRAM Static Random Access Memory Read/write very fast Needs 6 transistors thus high cost and needs more area Do not need to refresh Low power consumption Implementation technology CMOS Construct cache memory DRAM DRAM Dynamic Random Access Memory Needs 1 transistor and 1 capacitor Lower cost and compact Each bit must be refreshed periodically Implementation technology CMOS Construct Main Memory Fast Page Mode conventional DRAM requires that a row and column be sent for each access FPM works by sending the row address just once for many accesses to memory in locations near each other, improving access time. That is Row address is decoded once with varied Column address decoded to access different bytes on the same row.(見54範例5.1) Extended Data Out (EDO) DRAM EDO DRAM also called hyper page mode DRAM EDO memory has had its timing circuits modified so one access to the memory can begin before the last one has finished (note: conventional DRAM needs some delay between two consecutive accesses) SDRAM Support burst operation Auto Column Address increment, that is do not need external CAS cycle time to select column address Interleaving memory contains two banks of memory internally instead of one This allows the second bank to be precharging (RAS and CAS activation) while the first bank is transferring data Will replace older DRAM technologies DDR SDRAM Double data rate SDRAM Access data both as rising and falling edge of clock Thus d