一种适用于低功耗超长指令字dsp处理器的硬件循环缓冲-uicece.pdfVIP

第 30 卷 　第 5 期 电 子 器 件 Vol. 30 　No . 5 20 07 年 10 月 　　　 Ch inese J ou r nal Of Elect ro n D evices 　　 Oct . 2 007 3 Har dwar e oop Buf fer Design f or ow2Power V IW DSP Pr oce ssor s S U Ye2h ua , I U J i a n , C H E N J i e ( I nst i tut e of M ic r oel ect r onics of Chi n ese Ac a demy o f Sci en ce Be ij i ng , 100029 Chi n a) Abstr act :An ar chit ect u r e an d de si gn of har dwar e lo op b uffer for a V IW D SP i s p r ovi ded . Due to t he char 2 act er ist ic of f r equen t r ep eti tions of a few fi xed al gorit hm s in t he D SP p r o gr am , a sp ecial h ar dw ar e mo dul e for ha ndlin g t he r ep eti tion i s de si gned to eli minat e t he st all o f pip eli ne caused b y f et chi ng t he loop in st r uc2 t ion s i n t his D SP ar chit ect ur e . And t he D SP pe rformance i s i mp roved si nce t he loop i s ha ndled w it h zero o 2 ver2head . In or der t o mini mize t he h ar dw ar e overh ead , t he rep et ition s ar e divi de d int o tw o ki nd s accor di ng t o t he l engt h of t h em and ha ndled discri mi nat in gly . Th e r esul t show s t hat t h e j u mp of loop i s op erat ed in a sep ar ate mo dule wit hou t st all of p ip eli ne an d t hu s t he p erformance i s i mp roved . The ar ea o f t h e ha r dw ar e loop b uffer i s 3 . 8 k lo gic gates . Key wor ds :V SI ; har dwar e loop ; zer o over head ; D SP ; in st ruction b uffer ; V IW E EACC :257 0 一 种 适 用 于 低 功 耗 超 长 指 令 字 DSP 处 理 器 的 3