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BBT3821-JH;BBT3821LP-JH;中文规格书,Datasheet资料
BBT3821
®
Data Sheet July 20, 2005 FN7483.2
Octal 2.488Gbps to 3.187Gbps/ • 0.13mm Pure-Digital CMOS Technology
Lane Retimer • 1.5V Core Supply, Control I/O 2.5V Tolerant
Features • Clock Compensation
• 8 Lanes of Clock Data Recovery and Retiming; 4 in • Tx/Rx Rate Matching via IDLE Insertion/Deletion up to
Each Direction ±100ppm Clock Difference
• Differential Input/Output • Receive Signal Detect and 16 Levels of Receiver
Equalization for Media Compensation
• Wide Operating Data Rate Range: 2.488Gbps to
3.1875Gbps, and 1.244Gbps to 1.59325Gbps • CML CX4 Transmission Output with 16 Settable Levels of
Pre-Emphasis, Eight on XAUI Side
• Ultra Low-Power Operation (195mW typical per lane,
1550mW typical total consumption) • Single-Ended or Differential Input Lower-Speed Reference
Clock
• Low Power Version Available for LX4 Applications
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