16位双译码器的VHDL实现.docx

16位双译码器的VHDL实现软件：Quartus ii 8.1设计思路：先设计一个2-4译码器，在2-4译码器的基础上设计一个8-256双译码器，然后在8-256双译码器的基础上设计出16-65536双译码器。双译码器需要与门阵列，而且与门阵列的设计才是此次设计的难点。为简化设计，与门阵列单独设计，本文先设计了4*4的与门阵列，然后将4*4的与门阵列扩展成4*16的与门阵列，然后又将4*16的与门阵列扩展成16*16的与门阵列，然后又将16*16的与门阵列扩展成了16*256的与门阵列，最后又将16*256的与门阵列扩展成了256*256的与门阵列。首先，先设计一个2-4译码器，代码如下：libraryieee;use ieee.std_logic_1164.all;entity decoder2to4 is port(en:instd_logic;x:in std_logic_vector(1 downto 0);y:out std_logic_vector(3 downto 0));end decoder2to4;architecturertl of decoder2to4 isbeginprocess(en,x)beginif(en=1)thencase x iswhen 00 = y=0001;when 01 = y=0010;when 10 = y=0100;when 11 = y=1000;when others = y=0000;end case;elsey=0000;end if;end process;endrtl;由2-4译码器扩展得到4-16双译码器需要用到4*4的与门阵列，所以需要设计一个4*4的与门阵列，代码如下：libraryieee;use ieee.std_logic_1164.all;entity and4mul4 isport(x:instd_logic_vector(3 downto 0);y:in std_logic_vector(3 downto 0);z:out std_logic_vector(15 downto 0));end and4mul4;architecture structure of and4mul4 iscomponent and2to1port(a,b: in std_logic;y: out std_logic);end component;beging1:fori in 3 downto 0 generateu1:and2to1 port map (x(0),y(i),z(i));end generate;g2:fori in 3 downto 0 generateu2:and2to1 port map (x(1),y(i),z(4+i));end generate;g3:fori in 3 downto 0 generateu3:and2to1 port map (x(2),y(i),z(8+i));end generate;g4:fori in 3 downto 0 generateu4:and2to1 port map (x(3),y(i),z(12+i));end generate;end structure;其中，与门and2to1的代码如下：libraryieee;use ieee.std_logic_1164.all;entity and2to1 isport(a,b: in std_logic;y: out std_logic);end and2to1;architecturertl of and2to1 isbeginprocess(a,b)variable comb : std_logic_vector(1 downto 0);begincomb := a b;case comb iswhen 00 = y = 0;when 01 = y = 0;when 10 = y = 0;when 11 = y = 1;when others = y = X;end case;end process;endrtl;由2-4译码器及4*4的与门阵列，扩展成4-16双译码器，代码如下：libraryieee;use ieee.std_logic_1164.all;entity dec4to16 isport(en:instd_logic;x:in std_logic_vector(1 downto 0);y:in std_logic_vector(1 downto 0);z:out std_logic_vector(15 downto 0));end dec4to16;architecture structure of dec4to16 iscompo