内存时序的调节（Memory timing adjustment）.docVIP

内存时序的调节（Memory timing adjustment） The timing of the memory, it is a kind of general parameters stored in the memory of the SPD. We see DDR3 as the timing of the memory 7-7-7-20, often 8-8-8-22, 9-9-9-24 first introduced below, each part representing the meaning of small. First give a complete memory timing (cases):7-7-7-20-4-89-10-7-20-0 1T, followed by the corresponding sequence introduced. 1.DRAM CAS Latency (tCL): CAS memory Latency refers to the latency memory read and write operation front row address controller, the parameters have great influence on memory bandwidth, smaller memory performance is high, whereas the lower, the higher the frequency of the memory operation parameters usually need to set the DDR3, according to the different physical memory, conservative setting is usually 7-9, too you can set different Cl values according to their own physical memory. 2.DRAM RAS to CAS Delay (tRCD): addressed to the column addressing delay time, the parameter setting of the memory bandwidth affect larger, smaller values better performance is usually conservative set 7-9. 3.DRAM RAS PRE Time (tRP): the memory address controller for pre charging time, the parameter setting has greater influence on memory bandwidth, the smaller the better numerical performance, conservative setting is usually 7-9, the number usually can be set to DRAM RAS to CAS Delay 1 numerical. 4.DRAM RAS ACT Time (tRAS): the shortest cycle memory active to precharge, the value have little effect on memory bandwidth, conservative set is usually 20-24. 5.DRAM RAS to RAS Delay (tRRD): unit to unit delay, the smaller the value the better, that is set to 5-7. 6.DRAM REF Cycle Time (tRFC):SDRAM refresh cycle time, the larger impact on memory bandwidth, usually set to 60, the relaxation parameters can be appropriate to enhance memory overclocking frequency, such as when the DDR3 memory overclocking above 2000MHz frequency is proposed, the value up to 88 or more. 7.DRAM WRITE Recovery Time (tWR): write r