主板上电时序分解（Time series decomposition of mainboard）.docVIP

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主板上电时序分解（Time series decomposition of mainboard）.doc

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主板上电时序分解（Time series decomposition of mainboard）

主板上电时序分解（Time series decomposition of mainboard） Decomposition of time series on mainboard.Txt 1, after loading the battery first sent to 3V_BAT RTCRST#, RTC is Real Nanqiao; Time Clock, for the real-time clock; rst is reset, meaning reset (CMOS battery or CMOS jumper for zero when VCCRTC is low (1 foot jumper detection points: CMOS, RTCRST#), the CMOS circuit reset state, i.e. CMOS messages lost. VCCRTC is Real Time Clock VCC acronym, meaning real time clock (positive) 3V_BAT ) is the power supply voltage of the battery, or VCCRTC, in the standby state, if the battery or no electricity, the power is turned on, the first call the conversion of +3VSB to replace the battery, 3V_BAT 2, the crystal provides 32.768KHz frequency to the South bridge; 3, the motherboard 1117 chip +5VSB conversion +3VSB IO +5VSB check is normal, if normal is issued by RSMRST#, SB OK Southbridge standby voltage; Stand By, commonly known as RSMRST# Resume standby voltage Well Reset acronym, meaning for the resumption of normal reset. Resume means restart, reset. RSMRST# is the norm for the recovery of the reset signal, reset all power supply recovery logic, at least the effective 10ms signal to act, when lifting effectively, hang up rsmrst# well reset = = resume active low reset for Southbridge sleep wakeup logic. If it is low, the South Bridge ACPI controller is always in the reset state and will not be powered on of course. 4 south, sending SUSCLK (32KHz); SUSCLK:Suspend Clock, This clock is an output of the RTC generator circuit to generator around use by other chipsfor refresh clock SUSCLK hang: this clock is the clock signal generated by the RTC clock generator chip clock output 5, press the power switch, sending the PWRBTN# to IO; PWRBTN# is the power button, if the system is in a sleep state, then the signal will trigger a wake-up event, if PWRBTN# has XXXXXX more than 4S, regardless of whether the system is in the S0, S2, S3, S4, will be unconditionally transferred to S5 state 6, IO r